Design of a New Step-Up DC-DC Converter with High Voltage Gain for PV Power Application
Abstract— This paper presents a single switch, high step-up, non-isolated dc-dc converter suitable for PV power application. The proposed converter is composed of a coupled inductor, a passive clamp circuit, a voltage multiplier cell and voltage lift circuit. The passive clamp recovers the leakage inductance energy of the coupled inductor and limits the voltage spike on the switch. The configuration of the passive clamp and voltage multiplier circuit increases the voltage gain. A high voltage gain without a large duty cycle, a low turn ratio for the coupled inductor, low voltage stress on the switch, low voltage stress on the diodes, leakage inductance energy recovery and high efficiency are the benefits of this converter. The steady state operation of the converter in the continuous conduction mode (CCM) is discussed and analyzed. Finally the validity of the proposed converter is confirmed by the simulation results via PSIM software.
Keywords—DC-DC converter; Step-up; High voltage gain; PV power application
I. Introduction
Nowadays reducing of fossil fuels resources and their environmental consequences have made it necessary to benefit from clean energy sources such as wind and solar. Therefore, distributed generation (DG) systems based on renewable energy sources have attracted the researchers attention. The DG systems include photovoltaic (PV) cells, fuel cells and wind power [1-3]. However, the output voltages of these sources are not large enough for connecting to ac utility voltage. PV cells can be connected in series in order to obtain a large dc voltage. However, it is difficult to ignore the shadow effect in PV panels [4]. High step-up converters are a suitable solution for the aforementioned problem. DC-DC converters can boost and regulate the output voltage of PV panels [5].
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In renewable energy systems, when galvanic isolation is not required, the conventional boost converter appears as the first choice. However, extreme duty ratio and consequently low efficiency are the main drawbacks at high output voltage gain [6]. Recently, several DC/DC converters have been proposed to increase the output voltage gain [7].
Switched inductors and switched capacitors structures are common as well [8]. The current stress on the main power devices is high in switched inductor structures while the high voltage stress is the main problem in switched capacitor based circuits [9]. Coupled inductor based boost converters are proposed to solve the aforementioned problems [10-16]. The leakage current of the coupled inductor is restored via active or passive clamps. Single switch coupled inductor based converters are also proposed in the literature. Since the leakage inductor of coupled inductors is very low, the input current is pulsating with an undesirable current ripple. The peak current of the leakage inductor passes through the main power switch which deteriorates the overall efficiency. By cascading boost converters, high output voltage gain can be achieved. However, too many components will be used in the circuit structures which increase the complexity of the circuit and decrease the total efficiency [16]. Therefore, they are not very efficient in processing energy. Some novel structures of high step up converters are also presented in [10] and [17].
This paper proposes a new high step-up DC–DC boost converter topology integrating coupled inductor, voltage multiplier cell and the voltage lift capacitor to further increase the voltage gain. The coupled inductor can be designed to extend the static gain and the voltage multiplier cell with voltage lift capacitor offers additional voltage gain. The energy stored in the leakage inductor of the coupled inductor can be recycled through the passive voltage clamp circuit. This causes the spike on power switch to be decreased and conduction loss is decreased, hence the efficiency is increased. The presented converter benefits from numerous advantages such as high output voltage gain without a large duty cycle, a high conversion ratio, low voltage stress on the switch, low voltage stress on the output diode, a wide CCM operation, leakage inductance energy recovery and high efficiency.
Fig. 1. Circuit configuration of proposed converter.
The reminder of the paper is organized as follows. Section II introduces new high step-up DC–DC boost converter topology. In this section the steady-state analysis of the presented converter are discussed in details. Design procedure of the proposed converted is presented in sections III. Section IV is about comparison study and Simulation results are provided in section V. Finally, section VI concludes this paper.
II. Operating Principle of The Proposed Converter
Fig. 1 shows the circuit configuration of the proposed
converter. The coupled inductor is shown with its equivalent
circuit including an ideal transformer, the magnetizing
inductance L_{m} and the leakage inductance L_{lk}. N_{P} and N_{S} are
the number of primary and secondary winding turns of an
ideal transformer, respectively. C_{1} is a clamp capacitor, C_{3},
C_{4} are switched capacitors, C_{2} is a voltage lift capacitor,
and C_{O} is an output capacitor. D_{1} is a clamp diode, D_{O} is the
output diode and D_{2}, D_{3}, D_{4} are blocking diodes. The proposed converter is suitable for PV power system applications where each PV module can be independently connected to the presented converter.
In order to simplify the circuit analysis of the proposed converter, the following assumptions are considered.
1) All components are ideal, and all the parasitic
parameters are ignored.
2) The capacitors C_{1} ~ C_{4} are large enough that the voltages across of them are assumed as constant in each switching period.
3) The turn ratio n of the coupled inductor is equal to N_{S}/N_{P}.
The following discussion is confined to continuous conduction mode (CCM) operation in one switching period. Some typical steady state waveform of the proposed converter in CCM operation is shown in Fig. 2, and the corresponding equivalent circuits are shown in Fig. 3. The operating modes are described as follows:
Mode 1 [t_{0},t_{1}]: In this mode, the switch S is turned on, and diodes D_{2} and D_{3} are on. The current-flow path is shown in Fig. 3(a). The current of magnetizing inductor Lm is increased and leakage inductor current L_{k} is increased both linearly. The capacitor C_{2}, C_{3} and C_{4} are charged and the output capacitor C_{O} is discharged to the load. This mode finishes when the inductor currents i_{lk} and i_{lm} becomes equal.
Mode 2 [t_{1},t_{2}]: During this time interval, the switch S is still on and the diodes D_{1}, D_{4} and D_{O} are off and the diodes of D_{2} and D_{3} are turned on as shown in Fig. 3(b). The magnetizing and leakage inductors are charged by the input source. Capacitor C_{2} and C_{3} is charged by the secondary side current of the coupled inductor and the energy stored in capacitor C_{1}. The output capacitor provides energy to the load. This mode is finished when the switch S is turned off.
Mode 3 [t_{2},t_{3}]: As it is shown in the Fig. 3(c), the switch S is turned off, and diodes D_{1}, D_{2}, D_{3} and D_{O} are conducting. The leakage inductor current is decreased linearly. Capacitors
Fig. 2. Some typical waveforms of the proposed converter at CCM operation.
of C_{1} and C_{3} are charged through diodes D_{1} and D_{3} respectively. Capacitors C_{2} and C_{4} are discharged to the load through diode D_{O}. This mode ends when the magnetizing and leakage inductor currents become equal.
Mode 4 [t_{3},t_{4}]: During this time interval, the switch S is off, and diodes D_{1}, D_{4} and D_{O} are conducting and diodes D_{2} and D_{3} are off. In this mode, the current of the leakage inductance i_{lk} is less than the current of the magnetizing inductance i_{Lm}. The current flow path is shown in Fig. 3(d). The leakage inductor is demagnetized to capacitor C_{1} through diode D_{1}. Capacitors C_{2}, C_{3} and C_{4} are discharged to the load through diodes D_{4} and D_{O}. This mode ends when diode D_{1} is turned off.
Mode 5 [t_{4},t_{5}]:As shown in Fig. 3(e), in this mode diodes D_{4} and D_{O} are turned on and the switch S is still off. The magnetizing and leakage inductor currents are decreased linearly and the energy of the magnetizing inductance, leakage inductance and input source Vin along with C_{2} , C_{3} and C_{4} is delivered to the load. Also the capacitor C_{1} is discharged. This mode ends by turning switch S on again and the next switching period starts.
In order to simplify the analysis, the leakage inductance of the coupled inductor is neglected in the steady-state analysis. Also, the losses of the power devices are not considered. Only stages 2, 4 and 5 are considered for CCM operation because the time durations of stages 1 and 3 are short significantly. At stage2, the main switch S is turned ON, the magnetizing inductance L_{m} is charged by the input dc source V_{in}. The following equations for Lm can be written from Fig. 3(b):
(1)
(2)
And the voltage of V_{C3} can be expressed by:
(3)
During stage 4 and 5, the main switch S is in the OFF state and magnetizing inductance is discharged. The voltages across the L_{m} can be obtained by:
(4)
(5)
In mode 4, the following equations for the capacitor voltages can be expressed:
(6)
In mode 5, the following equation, according to Fig. 3 (e), can be derived:
(7)
Using the inductor volt-second balance principle to the magnetizing inductor L_{m}, the following equations can be expressed as:
(8)
From (8), the voltage across capacitor C_{1} is derived as follows:
(9)
Fig. 3. Current-flow path of operating modes during one switching period at CCM operation. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5
Fig. 4. Voltage gain as a function of D and n values
Fig. 5. Voltage gains as a function of the duty ratio of the proposed converter, and the other converters under turn ratio: n=2.
According to (9) and (1), the voltage of the capacitor C_{2} will be written:
(10)
By substituting (9) and (10) into (3), the voltage of the capacitor C_{3} is obtained as:
(11)
According to (4), (5) and (11), and simplifying the equations, the voltage of the capacitor C_{4} can be expressed:
(12)
From (6), (9), (10) and (12), the DC voltage gain M_{CCM} can be achieved as follows:
(13)
The coupled inductor turns ratio n can be adjusted to achieve the desired voltage conversion ratio without resorting to extreme duty cycle operation. The relationship between the static gain, duty cycle and turns ratio is plotted in Fig. 4.
When the coupled inductor turns ratio is zero, the voltage gain of the proposed circuit is higher than that of the conventional boost converter. The voltage gain increases significantly at higher turns ratio.
Fig. 5 shows voltage gains comparison of the proposed converter and presented converters in [13-15]. As shown in this picture, the voltage gain of the proposed converter is more than the other converters.
III. Design Procedure of The Presented Converter
A. The Capacitors Design
Equations (9)-(12) are used to obtain the voltage of the capacitors C_{1}, C_{2}, C_{3} and C_{4}. Since the charges absorbed or produced by the capacitors C_{1}, C_{2}, C_{3} and C_{4} are all equal, the size of these capacitors are obtained as:
(14)
where I_{O} is the load current, T_{S} is the switching period, and r is the ripple factor of the capacitor voltage, which is equal to the ratio of the capacitor peak-to-peak ripple voltage to the capacitor average voltage. V_{i} is the average voltage of the capacitor.
B. The Magnetizing Inductor current ripple
In terms of the operating principles, the current ripple on the magnetizing inductor is expressed as:
(15)
(16)
C. Voltage Stress Analysis
In order to choose the appropriate semiconductors of the presented converter, their voltage stresses should be obtained. According to the operation principle of the proposed converter, the voltage stresses of the switches and diodes can be formulated as follows:
(17)
(18)
(19)
(20)
(21)
(22)
IV. Comparision Study
Some features of the proposed converter and other presented converters in [11], [13]-[15] are collected in Table I. As shown in this table, the voltage gain of the proposed converter is more than the others and the voltage stress on the main switch in the proposed converter under the same voltage gain is less than the converter in [15]. However the suggested converter has some advantages such as high voltage gain, low current ripple, recycled leakage inductor and high efficiency.
V. Simulation Results
In order to verify the steady state analysis, simulation results of the proposed converter in CCM operation with PSIM software is prepared. The circuit parameters are given in Table II.
The input and output voltage waveforms are shown in Fig. 6(a), 6(b). The output voltage is equal to 303 V. The capacitors C_{1}, C_{2}, C_{3} and C_{4} voltage waveforms are shown in Figs. 6(c), 6(d). The leakage current of the coupled-inductor is shown in Fig. 6 (e). The obtained waveform is similar to Fig. 2 and the analysis of the presented converter. The voltage and current stress of the power switch is also depicted in Fig. 6(f). The maximum voltage of the power switch is 67V. It is also shown that there are no voltage spikes on the power switch.
According to Fig. 6(g), 6(h), 6(i) and 6(j) the voltages and currents of the diodes D_{1}, D_{2}, D_{3} and D_{4} are also depicted. The
TABLE I. The Comparison Between the Proposed Converter and Some other Converters.
Reference |
Number of Components | Voltagegain | Voltagesressonswitch | |||
Diode | Cap | Switch | Core | |||
Proposed converter | 5 | 5 | 1 | 1 | ||
Converter in [13] | 4 | 4 | 1 | 1 | ||
Converter in [15] | 4 | 4 | 1 | 1 | ||
Converter in [11] | 3 | 4 | 1 | 2 | ||
Converter in [14] | 3 | 3 | 1 | 1 |
TABLE II. The Circuit Parameters of The Simulated Prototype.
Specifications | Values |
Input Voltage | 23 V |
Output Voltage | 303V |
Capacitors | C_{1}, C_{2}, C_{3}, C_{4} = 47uF
C_{O}=180 uF |
Coupled-inductor | L_{m}=200uH
n=N_{S}/N_{P}=2 |
Switching frequency | 50 kHz |
Output Power | 200 W |
Duty cycle | 0.65 |
voltage stresses of the diodes validate the analysis of the presented converter.Fig.7 shows the efficiency of the proposed converter for several output powers. It is considered that r_{DS} is , r_{D1}, r_{D2}, r_{D3}, r_{D4}, r_{L1}, r_{C1}, r_{C2}, r_{C3} and r_{C4} are. The threshold voltages of the diodes D_{1}, D_{2}, D_{3}, D_{4} and D_{O} are also considered to be 0.7V, 1.2V, 0.8V, 0.8V, 1.2V respectively. The maximum efficiency of the proposed converter under the output power of 75W is 95% and for the output power of 200W, the efficiency is approximately 92.3%.
According to the simulation results, the analysis and the feasibility of the proposed converter are validated. Various advantages of the presented converter make it suitable for several applications such as PV panels.
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(j)
Fig. 6. Simulation results of the proposed converter under the output power of 200W
Fig. 7. Simulation efficiency of the proposed converter
VI. Conclusion
This paper proposed a new high step up DC-DC converter. By using a coupled inductor and utilizing the voltage multiplier cell and voltage lift techniques, a high voltage gain is achieved. Clamp circuit in this converter is employed to recycle the stored energy in the leakage inductor. Therefore the voltage stress on the main switch is reduced and the efficiency of the proposed converter is increased. Continues conduction mode operation (CCM), voltage gain, voltage stress of the semiconductors in steady state analysis are discussed in this paper. Finally voltage gain of this converter is compared with some other converters. The proposed converter is simulated under the output power of 200W in PSIM to validate the analysis.
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